The Global system for Mobile Communications (GSM) and the Digital Cellular system (DCS) for use in the second-generation cellular phones according to the present global mainstream cellular phone system have already employed four radio frequency bands of 800, 900, 1800, 1900 MHz in order to provide a wide user area. In the future, as second-generation cellular phones shift to third-generation cellular phones based on Enhanced Data GSM Environment (EDGE), CDMA (Code Division Multiple Access), and Wideband CDMA (WCDMA) systems, dual terminals that are individually capable of using second- and third-generation services will be put into service, which will require that cellular phones be compatible with 1.7 GHz and 2 GHz bands in addition to the above four bands.
The study of high-speed systems as next-generation mobile communication systems for achieving transmission rates ranging from several tens to 100 Mbps has also been started. In addition to these public mobile communication systems, efforts to incorporate a plurality of wireless systems such as wireless LAN according to IEEE802.11, Bluetooth, GPS, and terrestrial digital TV into cellular terminals have been accelerated. These applications will be added as standard features to cellular phones in the new future. The radio frequencies of these wireless systems span a wide range from 400 MHz to 5.8 GHz, and the front end of RF chips needs to have a circuit compatible with those frequency bands.
The frequency bands can be covered by a single circuit if its gain in desired frequency bands is sacrificed. Generally, however, a plurality of bands are available and selectively used to cover a wide frequency range (see, for example, Non-patent document 1).
Non-patent document 1 discloses a multiband-compatible chip having a plurality of parallel-connected amplifiers having matching circuits for respective frequencies to cover a plurality of frequency bands. Each of the circuits corresponding to a desired frequency band is activated one at a time, with the other circuits being kept in a shut-off state.
Another example which handles a plurality of frequency bands is a system proposed for suppressing input signals that will not be used by means of filters (see, for example, Patent document 1).
The example disclosed in Patent document 1 relates to a television receiver and comprises a wideband receiving circuit for receiving all terrestrial broadcasts and CATV channels.
FIG. 1 is a circuit diagram of a band switching circuit proposed in Patent document 1. Filter FL1 for passing a signal in a first frequency band and filter FL2 for passing a signal in a second frequency band are connected in series to each other. Filter FL1 is a high-pass filter comprising capacitors C21, C22, C23 and inductors L21, L22 for passing a signal in a low frequency range (e.g., 90 MHz and higher).
Filter FL2 is a high-pass filter comprising capacitors C24, C25, C26 and inductor L23 for passing a signal in a high frequency range (e.g., 470 MHz and higher). Switch device (PIN diode) SW1 is connected parallel to second filter FL2. When filter FL2 is required, switch 3 is turned off. When filter FL2 is not required, switch 3 is turned on.
Filter FL2 includes switch device (PIN diode) SW2 for turning on and off a series-connected resonant circuit of capacitor C25 and inductor L23. When second filter FL2 is not required, switch SW2 is turned off to disconnect the series-connected resonant circuit.
When the band switching circuit is to receive a signal in a frequency band ranging from 90 to 470 MHz which is input from input terminal IN, switch device SW1 is turned on and switch device SW2 is turned off to put only filter FL1 in operation while keeping filter FL2 out of operation, thereby outputting the signal from output terminal OUT while bypassing filter FL2. Therefore, only a signal of 90 MHz or higher from filter FL1 is output from output terminal OUT to an external circuit.
When the band switching circuit is to receive a signal in a frequency band ranging from 470 MHz to 770 MHz, switch device SW1 is turned off and switch device SW2 is turned on to put filter FL1 and filter FL2 simultaneously in operation. Therefore, a signal of 90 MHz or higher that has passed through filter FL1 is processed by filter FL2 into a signal of 470 MHz or higher, which is output from output terminal OUT to the external circuit.
Communication schemes using advanced modulation processes such as Quadrature Amplitude Modulation (QAM) and orthogonal frequency modulation (OFDM) have been studied for use in high-speed systems in recent years.
Since these communication schemes need a vast amount of digital processing for signal demodulation, attempts have been made to employ ultrasmall gate CMOS devices for use in digital baseband circuits having low power consumption requirements. As the devices become smaller and smaller in size, the power supply voltage therefor tends to be lower—from 3.3 V for 0.35 μm, 2.5 V for 0.25 μm, 1.8 V for 0.18 μm, 1.2 V for 0.13 μm, 1.0 V for 90 nm.
To reduce the cost of chips, the tendency to produce an RF circuit and a digital circuit as one chip is being accelerated. Accordingly, RF circuits that are operable under low voltages are needed. One of the greatest concerns in achieving lower RF circuit voltages is a dynamic range. The dynamic range may be considered to be from the maximum signal level that can be handled, to less a lower noise level.
Generally, a circuit scheme for varying the gain of an amplifying circuit depending on the intensity of an input signal is employed to keep a wide dynamic range (see, for example, Patent document 2).
FIG. 2 is a circuit diagram of a variable-gain amplifying circuit disclosed in Patent document 2. Gain control amplifying circuit 201 comprises amplifying transistor unit 202 and variable attenuators 203a, 203b disposed in a front stage thereof.
Amplifying transistor unit 202 includes amplifying MOSFETs Q30, Q31 and amplifying MOSFETs Q32, Q33 that are connected parallel thereto. Differential input signals F2a, F2b that are input to input terminals INa, INb are supplied through respective variable attenuators 203a, 203b to the gates of amplifying MOSFETs Q30, Q32.
First bias voltage Vbias1 is supplied through resistor R11 to the gates of amplifying MOSFETs Q31, Q33, and second bias voltage Vbias2 is supplied through resistor R12 to the gates of amplifying MOSFETs Q30, Q32.
MOSFETs Q31, A33 have respective drains connected to power supply terminal Vdd through load inductors L31, L32. The drains of MOSFETs Q31, A33 output differential output signals Fouta, Foutb from output terminals OUTa, OUTb through output coupling capacitors Couta, Coutb.
The overall gain of gain control amplifying circuit 201 is controlled by varying the attenuations of variable attenuators 203a, 203b which are connected between the gates of amplifying MOSFETs Q30, Q32 of amplifying transistor unit 202 and input terminals INa, INb.
Each of variable attenuators 203a, 203b includes input coupling capacitor Cin whose capacitance is variable and which is connected between input terminal INa (INb) and signal propagation path SPR leading to the gate of MOSFET Q32 (Q30).
Input coupling capacitor Cin comprises a plurality of capacitors C51 through C54 and n-channel switching MOSFETs Q51 through Q54. The capacitance of input coupling capacitor Cin is varied when these MOSFETs are rendered conductive and nonconductive by coupling capacitance control signals GC11 through CG14.
Signal propagation path SPR is connected to power supply ground by a plurality of (four in FIG. 2) parallel attenuating units comprising respective attenuating capacitors C41 through C44 and switching MOSFETs Q41 through Q44 connected in series thereto.
Switching MOSFETs Q41 through Q44 have respective gates supplied with respective attenuation control signals GC1 through CG4 for rendering switching MOSFETs Q41 through Q44 conductive and nonconductive.
High-frequency input signal F2a (F2b) applied to input terminal INa (INb) is supplied through input coupling capacitor Cin and signal propagation path SPR to the gate of amplifying MOSFET Q32 (Q30).
If attenuation control signal GC1 reaches a high level to render MOSFET Q41 conductive, then part of the energy of the high-frequency signal that is propagated through signal propagation path SPR is absorbed through attenuating capacitor C41 and MOSFET Q41 into ground.
Specifically, attenuating capacitor C41 has a function to short an AC component of the high-frequency signal to ground GND. The amount of energy that is absorbed is determined depending on the capacitance value of attenuating capacitor C41.
By increasing the number of attenuating capacitors by rendering other transistors conductive, the amount of absorbed energy is increased, resulting in an increase in the attenuation.
If the variable attenuators are designed to increase the capacitance values of attenuating capacitors C41 through C44 in a binary fashion of 1:2:4:8, for example, and also if the widths of the gates of switching MOSFETs Q41 through Q44 are of the same ratio, then the attenuation of variable attenuator 203a (203b) can be increased linearly by using attenuation control signals GC1 through CG4 in appropriate combinations.
Specifically, the attenuation is of the lowest level when all MOSFETs Q41 through Q44 are rendered nonconductive, and is linearly increased when MOSFETs Q41 through Q44 are rendered nonconductive in combinations.
Therefore, the amplitude of the input high-frequency input signal is linearly varied by attenuator 203a (203b), and then amplified at a fixed gain by amplifying transistor unit 202.
As a result, the gain of the overall amplifying circuit is linearly varied. Since the gain is increased by two cascaded MOSFETs Q30, Q31 of amplifying transistor unit 202, the variable range of the gain can be widened.
FIG. 3 shows a charge pump circuit as disclosed in Patent document 3 for boosting the control signals for signal switching circuits Q51 through Q54 shown in FIG. 2. The charge pump circuit stores electric charges in capacitive elements using a clock for thereby obtaining a potential higher than an input potential. The charge pump circuit comprises a plurality of boosting stages for higher boosting efficiency.
As shown in FIG. 3, the boosting circuit comprises n boosting stages CP1, CP2, . . . CPn. Each boosting stage CPk (k is 1, 2, . . . , n) comprises first charge pump 11 and second charge pump 13.
First charge pump 11 of boosting stage CPk comprises n-type MOSFET nQ1k, p-type MOSFET pQ1k, and pumping capacitor C1k. Second charge pump 13 of boosting stage CPk comprises n-type MOSFET nQ2k, p-type MOSFET pQ2k, and pumping capacitor C2k.
When clock CLK is of a power supply voltage (CLKbar is 0 V), n-type MOSFET nQ2k and p-type MOSFET pQ1k are rendered conductive, charging capacitor C2k to the potential of node NDk-1. The potential of the drain of p-type MOSFET pQ1k (the potential boosted by the clock provided by the charged potential of capacitor C1k) is transferred to node NDk.
When the clock is inverted to raise CLKbar to the power supply voltage (CLK is 0 V), n-type MOSFET nQ1k and p-type MOSFET pQ2k are rendered conductive, charging capacitor C1k to the potential of node NDk-1. The potential of the drain of p-type MOSFET pQ2k (the potential boosted by the clock provided by the charged potential of capacitor C2k) is transferred to node NDk.
Non-patent document 1: 2005 IEEE International Solid State Circuit Conference, SESSION 5, pp. 98-99 & 586
Patent document 1: JP-U No. 5-48440
Patent document 2: JP-A No. 2005-159803
Patent document 3: JP-A No. 2000-69745